Due on Monday.
Assignment 3: Design 4x1 and 8x1 mux using data flow and behavioural modelling in verilog. Assignment 4: Q 1 and 2 from exercise of Chapter 6 from book by Samir Palnikar.
Assignment 3: Design 4x1 and 8x1 mux using data flow and behavioural modelling in verilog. Assignment 4: Q 1 and 2 from exercise of Chapter 6 from book by Samir Palnikar.
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