Digital Design Update

Instructor: Ms. Sahar Waqar

Lab Instructor: *drumroll* Dr. Zohaa Qamar, Back with a Vengeance

Books:
1) Verilog HDL by Samir Pattnikar - Chapters 1 - 7
2) Advanced HDL Verilog by Michael Cilleti  - Selected text from this book

Lab Details: We will be using XiLinx software. The setup is worth 1.3 GB and it can not be emailed. I am trying to upload it to Dropbox or Google Drive but the prospects are terrible. Better to take it in USB from me. We must have it INSTALLED for the lab come Saturday inshaAllah.
The Lab will be on the first floor of EE Department.

Here are some details about the project:

1. Open the IDE.
2. File->New->Project
3. Family: Spartan3
4. Package: FT250
5. Speed: -5

Attendance Rule: For class, after five minutes from the start of class attendance will not be taken/considered. To sit for the exam, attendance must be atleast 75-80%. Otherwise Ms. Sahar will not allow you to sit for the exam.

General Rule: Pop Quizzes are possible.

Homework Update:

Assignment#1:
Search and compile definitions of the following terms:

1. Transistors
2. CMOS
3. FET
4. Verilog
5. HDL
6. VLSI
7. Flip-Flops: D, T, RS, JK
8. Latch
9. MOSFET

Assignment#2:
Make the Gate-Level, Data-Flow-Level and Behavior Level Models of the full adder in the Verilog syntax.

Both assignments are due Wednesday next week. (Undelayable - if that is a word)
Both assignments must be HANDWRITTEN and submitted in hard form.